EPOKA UNIVERSITY
FACULTY OF ECONOMICS AND ADMINISTRATIVE SCIENCES
DEPARTMENT OF BUSINESS ADMINISTRATION
COURSE SYLLABUS
2024-2025 ACADEMIC YEAR
COURSE INFORMATIONCourse Title: COMPUTER ORGANIZATION |
| Code | Course Type | Regular Semester | Theory | Practice | Lab | Credits | ECTS |
|---|---|---|---|---|---|---|---|
| CEN 219 | B | 3 | 3 | 0 | 0 | 3 | 5 |
| Academic staff member responsible for the design of the course syllabus (name, surname, academic title/scientific degree, email address and signature) | Dr. Florenc Skuka fskuka@epoka.edu.al |
| Main Course Lecturer (name, surname, academic title/scientific degree, email address and signature) and Office Hours: | B.Sc. Amela Rahimi arahimi17@epoka.edu.al , Thursday 10:00 |
| Second Course Lecturer(s) (name, surname, academic title/scientific degree, email address and signature) and Office Hours: | NA |
| Language: | English |
| Compulsory/Elective: | Compulsory |
| Study program: (the study for which this course is offered) | Bachelor in Business Informatics (3 years) |
| Classroom and Meeting Time: | E313 |
| Teaching Assistant(s) and Office Hours: | NA |
| Code of Ethics: |
Code of Ethics of EPOKA University Regulation of EPOKA University "On Student Discipline" |
| Attendance Requirement: | |
| Course Description: | Understanding of the inner-workings of modern computer systems and tradeoffs present at the hardware-software interface: Instruction set design and addressing modes, register transfer, internal CPU bus structure, ALU (microprogramming and hardwired control), computer arithmetic, memory system, input-output system and survey of real computers and microprocessors. |
| Course Objectives: | The main objective of the course is to introduce students to the computer organisation from hardware and programming . This course teaches students fundamental knowledge in computer architecture and microarchitecture. The course covers the basic organizations of computer systems including instruction- set architecture, execution pipeline, memory hierarchy, and I/O subsystem. It also addresses advanced processor microarchitecture issues such as dynamic instruction scheduling, branch prediction, lock-up free caches, instruction-level parallelism, multiple instruction fetch/issuing, speculative execution, etc. to improve computer processor performance. Shared-memory multiprocessor systems with coherent caches to reduce memory access latency are also covered. Finally, it outlines the verification issues of today's microprocessors. |
|
BASIC CONCEPTS OF THE COURSE
|
| 1 | Binary Number System: Understanding binary representation, conversion between binary and decimal, and basic binary arithmetic. |
| 2 | Data Representation: Learning how data types (integers, floats, characters) are represented in memory, including fixed and floating-point representation. |
| 3 | Computer Architecture: Familiarity with the basic structure of a computer, including the CPU, memory (RAM and cache), and I/O devices. |
| 4 | Instruction Set Architecture (ISA): Understanding the set of instructions that a CPU can execute, including operation codes (opcodes) and addressing modes. |
| 5 | Assembly Language: Gaining insight into low-level programming with assembly language, and how it translates to machine code. |
| 6 | Memory Hierarchy: Exploring the organization of memory (registers, cache, main memory, secondary storage) and concepts like access speed, size, and cost. |
| 7 | Pipelining: Learning the concept of instruction pipelining to improve CPU performance through parallel execution of instructions. |
| 8 | Control Unit and ALU: Understanding the role of the Control Unit and the Arithmetic Logic Unit (ALU) in executing instructions and performing calculations. |
| 9 | Input/Output Systems: Familiarity with how computers communicate with peripheral devices and the various methods (interrupts, polling) for handling I/O operations. |
| 10 | Performance Measurement: Learning how to measure and analyze computer performance |
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COURSE OUTLINE
|
| Week | Topics |
| 1 | Introduction: Digital computer generation, computer types and classifications, functional units and their interconnections, buses, bus architecture, types of buses and bus arbitration. Register, bus and memory transfer. |
| 2 | Central Processing Unit: Addition and subtraction of signed numbers, look ahead carry adders. Multiplication: Signed operand multiplication, Booths algorithm and array multiplier. Division and logic operations. Floating point arithmetic operation Processor organization, general register organization, stack organization. |
| 3 | Addressing modes. Assembler language. |
| 4 | Addressing modes. Assembler language. |
| 5 | Control Unit: Instruction types, formats, instruction cycles and subcycles ( fetch and execute etc) , micro-operations, execution of a complete instruction. |
| 6 | Hardware and microprogrammed control: microprogramme sequencing, wide branch addressing, microinstruction with next address field, pre-fetching microinstructions, concept of horizontal and vertical microprogramming. |
| 7 | Memory: Basic concept and hierarchy, semiconductor RAM memories, 2D & 2D memory organization. ROM memories. |
| 8 | Midterm Exam. |
| 9 | Cache memories: concept and design issues, performance, address mapping and replacement. |
| 10 | Virtual memory: concept implementation. Auxiliary memories: magnetic disk, magnetic tape and optical disks. |
| 11 | Input / Output: Peripheral devices, I/O interface, I/O ports, Interrupts: interrupt hardware, types of interrupts and exceptions. |
| 12 | Modes of Data Transfer: Programmed I/O, interrupt initiated I/O and Direct Memory Access, I/O channels and processors. Serial Communication: Synchronous & asynchronous communication, standard communication interfaces. |
| 13 | Pipelining: Basic and Intermediate Concepts. Instruction-Level Parallelism and Its Exploitation |
| 14 | Modern Multicore Architecture, Multiprocessors and Thread-Level Parallelism |
| Prerequisite(s): | Data Structures and Algorithms and programming knowledge is required. |
| Textbook(s): | 1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky and Naraig Manjikian, “Computer Organization and Embedded Systems”, Sixth Edition, McGraw, Hill, 2012. 2. Carl Hamacher, Zvonko Vranesic and Safwat Zaky, “Computer Organization”, Fifth Edition, Tata McGraw, Hill, 2002. |
| Additional Literature: | 1. William Stallings, “Computer Organization and Architecture – Designing for Performance”, Sixth Edition, Pearson Education, 2003. 2. Patterson, Computer Organisation and Design, Elsevier Pub. 2009 3. Mano,” Computer System Architecture”, PHI 4. John P Hays, “ Computer Organization”, McGraw Hill 5. Tannenbaum,” Structured Computer Organization’, PHI 6. P Pal Chaudhry, ‘ Computer Organization & Design’, PHI |
| Laboratory Work: | No |
| Computer Usage: | No |
| Others: | No |
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COURSE LEARNING OUTCOMES
|
| 1 | Knowledge of digital computer generation, computer types and classifications, functional units and their interconnections, buses, bus architecture, types of buses and bus arbitration. Register, bus and memory transfer. |
| 2 | Knowledge on Central Processing Unit: Addition and subtraction of signed numbers, look ahead carry adders. Multiplication: Signed operand multiplication, Booths algorithm and array multiplier. Division and logic operations. Floating point arithmetic operation Processor organization, general register organization, stack organization and addressing modes. |
| 3 | Ability to use on low level Assembler language. |
| 4 | Knowledge on Control Unit: Instruction types, formats, instruction cycles and subcycles ( fetch and execute etc) , micro-operations, execution of a complete instruction. Hardware and microprogrammed control: microprogramme sequencing, wide branch addressing, microinstruction with next address field, pre-fetching microinstructions, concept of horizontal and vertical microprogramming. |
| 5 | Knowledge on Memory: Basic concept and hierarchy, semiconductor RAM memories, memory organization. ROM memories. Cache memories: concept and design issues, performance, address mapping and replacement) Auxiliary memories: magnetic disk, magnetic tape. Virtual memory: concept implementation. |
| 6 | Knowledge about Input / Output: Peripheral devices, I/O interface, I/O ports, Interrupts: interrupt hardware, types of interrupts and exceptions. Modes of Data Transfer: Programme I/O, interrupt initiated I/O and Direct Memory Access, I/O channels and processors. |
| 7 | Knowledge about Communication protocols: Serial Communication: Synchronous & asynchronous communication, standard communication interfaces. |
| 8 | Knowledge about Pipelining: Basic and Intermediate Concepts. Instruction-Level Parallelism and its Exploitation. |
| 9 | Knowledge about modern multicore architecture, Multiprocessors and Thread-Level Parallelism |
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COURSE CONTRIBUTION TO... PROGRAM COMPETENCIES
(Blank : no contribution, 1: least contribution ... 5: highest contribution) |
| No | Program Competencies | Cont. |
| Bachelor in Business Informatics (3 years) Program | ||
| 1 | Identify activities, tasks, and skills in management, marketing, accounting, finance, and economics. | 4 |
| 2 | Apply key theories to practical problems within the global business context. | 5 |
| 3 | Demonstrate ethical, social, and legal responsibilities in organizations. | 4 |
| 4 | Develop an open minded-attitude through continuous learning and team-work. | 5 |
| 5 | Integrate different skills and approaches to be used in decision making and data management. | 5 |
| 6 | Combine computer skills with managerial skills, in the analysis of large amounts of data. | 5 |
| 7 | Provide solutions to complex information technology problems. | 5 |
| 8 | Recognize, analyze, and suggest various types of information-communication systems/services that are encountered in everyday life and in the business world. | 5 |
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COURSE EVALUATION METHOD
|
| Method | Quantity | Percentage |
| Midterm Exam(s) |
1
|
30
|
| Quiz |
2
|
10
|
| Final Exam |
1
|
40
|
| Attendance |
10
|
|
| Total Percent: | 100% |
|
ECTS (ALLOCATED BASED ON STUDENT WORKLOAD)
|
| Activities | Quantity | Duration(Hours) | Total Workload(Hours) |
| Course Duration (Including the exam week: 16x Total course hours) | 16 | 3 | 48 |
| Hours for off-the-classroom study (Pre-study, practice) | 15 | 1 | 15 |
| Mid-terms | 1 | 17 | 17 |
| Assignments | 2 | 10 | 20 |
| Final examination | 1 | 25 | 25 |
| Other | 0 | ||
|
Total Work Load:
|
125 | ||
|
Total Work Load/25(h):
|
5 | ||
|
ECTS Credit of the Course:
|
5 | ||
|
CONCLUDING REMARKS BY THE COURSE LECTURER
|
|
Students should attend at least 75% of the classes. However students should consider possible loss of specific evaluation in a certain day they are missing. Exam content: Content for exam questions will be developed from class sides, discussions. assignments and homework. Academic integrity: cheating, plagiarism or any other type of academic dishonesty is not tolerated. Each Student is responsible for understanding the Epoka University Discipline Regulation and Exam Rules. Grading: Students grade is not subject to negotiation; in case of perceived human error by the lecturer side, the student should submit their concern in writing and ask for reevaluation of the exam paper/assignment/homework. |